Integrated circuits including microprocessors often contain sub-circuits that generate multibit binary codes for controlling other sub-circuits within the integrated circuit. Often times, these integrated circuits require the averaging of two or more of the multibit binary codes, the result of which is used to control another sub-circuit. Typically, an adder sub-circuit and a divider sub-circuit operating together perform the function of averaging binary codes.
FIG. 1 illustrates relevant components of an integrated circuit 10 in block diagram form. Integrated circuit 10 includes sub-circuits 12-20. More particularly integrated circuit 10 includes first and second code generation sub-circuits 12 and 14, having outputs coupled to a pair of inputs of average code generation sub-circuit 16. Lastly integrated circuit 10 includes a sub-circuit 20 having an input which is coupled to the output of average code generation sub-circuit 16. For purposes of explanation, the term coupled circuits means that two circuits or sub-circuits that are directly or indirectly coupled together. For example, first code generation sub-circuit 12 is coupled to sub-circuit 20 although coupled via average code generation sub-circuit 16.
Average code generation sub-circuit 16 operates upon binary codes am-1:0 and bm-1:0. More particularly, average code generation circuit generates an average binary code cm-1:0 which represents the average of binary codes am-1:0 and bm-1:0. Average code generation sub-circuit 16 is a synchronous circuit and operates as a function of a clock signal (CLK) received thereby. In other words, average code generation sub-circuit 16 generates binary code cm-1:0 upon a falling or rising edge of the clock signal CLK. It is noted that first and second code generation circuits 12 and 14 are also shown to be synchronous sub-circuits. Average binary code cm-1:0 is provided to sub-circuit 20 which in turn performs some function in response to receiving cm-1:0.
FIG. 2 illustrates, in block diagram form, the relevant components of average code generation sub-circuit 16 of FIG. 1. More particularly, average code generation sub-circuit shown 16 in FIG. 2 includes an adder sub-circuit 22 coupled to a divider sub-circuit 24. The adder and divider sub-circuits 22 and 24, respectively, are shown as synchronous circuits in that they operate as a function of the clock signal CLK provided thereto. Adder sub-circuit 22 receives binary codes am-1:0 and bm-1:0 from first and second code generations sub-circuits 12 and 14, respectively. In response, adder sub-circuit 22 generates c′m-1:0 which represents an addition of binary codes am-1:0 and bm-1:0. Divider sub-circuit 24 operates to divide c′m-1:0 by two to generate average binary code cm-1:0.
One goal in integrated circuit design is to reduce the total substrate area occupied by the integrated circuit. Unfortunately, the adder and divider sub-circuits 22 and 24 may occupy a substantial area of the substrate upon which integrated circuit 10 is formed. Another goal in integrated circuit design is to reduce the complexity of sub-circuits. The adder and divider sub-circuits 22 and 24 are generally complex (i.e., they consist of a large number of interconnected gates) and require substantial design effort to implement and verify. Still yet another goal in integrated circuit design is to increase the speed at which the integrated circuit or sub-circuits thereof operate. Adder and divider circuits 22 and 24 are synchronous. A certain amount of time delay exists between generation of the average binary code cm-1:0 from the input binary codes am-1:0 and bm-1:0. This time delay is dependent upon the frequency of the clock signal CLK provided to adder and divider sub-circuits 22 and 24.